View ZL30414QGC_8588265.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. features ? meets jitter requirements of telcordia gr-253- core for oc-192, oc-48, oc-12, and oc-3 rates ? meets jitter requirements of itu-t g.813 for stm- 64, stm-16, stm-4 and stm-1 rates ? provides four lvpecl differential output clocks at 622.08 mhz ? provides a cml differential clock at 155.52 mhz ? provides a single-ended cmos clock at 19.44 mhz ? lock indicator ? provides enable/disable control of output clocks ? accepts a cmos reference at 19.44 mhz ? 3.3 v supply applications ? sonet/sdh line cards ? network element timing cards description the zl30414 is an analog phase-locked loop (apll) designed to provide jitter attenuation and rate conversion for sdh (synchronous digital hierarchy) and sonet (synchronous optical network) networking equipment. the zl30414 generates very low jitter clocks that meet the jitter requirements of telcordia gr-253-core oc-192, oc-48, oc-12, oc- 3 rates and itu-t g.813 stm-64, stm-16, stm-4 and stm-1 rates. the zl30414 accepts a cmos compatible reference at 19.44 mhz and generates four l vpecl differential output clocks at 622.08 mhz, a cml differential clock at 155.52 mhz and a single-ended cmos clock at 19.44 mhz. the output clocks can be individually enabled or disabled. the zl30414 provides a lock indication. june 2004 ordering information ZL30414QGC 64 pin tqfp -40 c to +85 c zl30414 sonet/sdh clock multiplier pll data sheet figure 1 - functional block diagram frequency detector vco c622op/n-a frequency lpf c622op/n-b c622op/n-c vdd gnd vcc c622op/n-d c19o c19oen c155op/n c155oen loop filter c622oen-c c19i c622oen-b bias c622oen-a c622oen-d & phase 19.44mhz 05 state machine lock reference bias circuit and dividers and clock drivers
zl30414 data sheet 2 zarlink semiconductor inc. figure 2 - tqfp 64 pin (top view) pin description pin description table pin # name description 1 gnd ground. 0 volt 2 vcc1 positive analog power supply. +3.3 v 10%. 3 vcc positive analog power supply. +3.3 v 10%. 4 5 c155on c155op c155 clock output (cml). these outputs provide a differential 155.52 mhz clock. 6 gnd ground. 0 volt 7 vcc2 positive analog power supply. +3.3 v 10% 8lpf low pass filter (analog). connect to this pin external rc network (r f and c f ) for the low pass filter. 9gnd ground. 0 volt 10 gnd ground. 0 volt 50 52 54 56 58 60 62 64 34 36 38 40 44 46 48 42 32 30 28 26 24 22 20 18 gnd vdd gnd vcc vdd vdd gnd gnd nc gnd gnd lock gnd c19o vcc gnd vdd c19oen nc nc ic nc vdd c19i vdd nc nc vdd gnd vcc c622op-c c622on-c gnd vcc c622op-b c622on-b gnd vcc c622op-a c622on-a gnd c622op-d c622on-d vcc 16 14 12 10 6 4 2 8 gnd vcc1 vcc c155on c155op gnd vcc2 lpf c622oen-b c622oen-d gnd bias c155oen c622oen-a c622oen-c gnd gnd gnd gnd gnd zl30414 65 - ep_gnd
zl30414 data sheet 3 zarlink semiconductor inc. 11 bias bias. see figure 13 for the recommended bias circuit. 12 c155oen c155o clock enable (cmos input). if tied high this control pin enables the c155op/n differential driver. pulling this input low disables the output clock and deactivates differential drivers. 13 c622oen-a c622 clock output enable a (cmos input). if tied high this control pin enables the c622op/n-a output clock. pu lling this input low disables the output clock without deactivati ng differential drivers. 14 c622oen-b c622 clock output enable b (cmos input). if tied high this control pin enables the c622op/n-b output clock. pu lling this input low disables the output clock without deactivati ng differential drivers. 15 c622oen-c c622 clock output enable c (cmos input). if tied high this control pin enables the c622op/n-c output clock.pul ling this input low disables the output clock without deactivati ng differential drivers. 16 c622oen-d c622 clock output enable d (cmos input). if tied high this control pin enables the c622op/n-d output clock.pul ling this input low disables the output clock without deactivati ng differential drivers. 17 gnd ground. 0 volt 18 vdd positive digital power supply. +3.3 v 10% 19 nc no internal bonding connection. leave unconnected. 20 nc no internal bonding connection. leave unconnected. 21 nc no internal bonding connection. leave unconnected. 22 vdd positive digital power supply. +3.3 v 10% 23 ic internal connection. connect this pin to ground (gnd). 24 nc no internal bonding connection. leave unconnected. 25 nc no internal bonding connection. leave unconnected. 26 c19oen c19o output enable (cmos input). if tied high this control pin enables the c19o output clock. pulling this pin low forces output driver into a high impedance state. 27 gnd ground. 0 volt 28 c19i c19 reference input (cmos input). this pin is a single-ended input reference source used for synchronization. this pin accepts 19.44 mhz. 29 vdd positive digital power supply. +3.3 v 10% 30 gnd ground. 0 volt 31 vdd positive digital power supply. +3.3 v 10% 32 gnd ground. 0 volt pin description table (continued) pin # name description
zl30414 data sheet 4 zarlink semiconductor inc. 33 gnd ground. 0 volt 34 vdd positive digital power supply. +3.3 v 10% 35 c19o c19 clock output (cmos output). this pin provides a single-ended cmos clock at 19.44 mhz. 36 gnd ground. 0 volt 37 lock lock indicator (cmos output). this output goes high when pll is frequency locked to the input reference c19i. 38 gnd ground. 0 volt 39 gnd ground. 0 volt 40 nc no internal bonding connection. leave unconnected. 41 gnd ground. 0 volt 42 vdd positive digital power supply. +3.3 v 10% 43 gnd ground. 0 volt 44 vcc positive analog power supply. +3.3 v 10% 45 gnd ground. 0 volt 46 vdd positive digital power supply. +3.3 v 10% 47 vcc positive analog power supply. +3.3 v 10% 48 gnd ground. 0 volt 49 vcc positive analog power supply. +3.3 v 10%. 50 51 c622on-d c622op-d c622 clock output (lvpecl) . these outputs provide a differential lvpecl clock at 622.08 mhz. unused lvpec l port should be left unterminated to decrease supply current. 52 gnd ground. 0 volt 53 vcc positive analog power supply. +3.3 v 10%. 54 55 c622op-c c622on-c c622 clock output (lvpecl) . these outputs provide a differential lvpecl clock at 622.08 mhz. unused lvpec l port should be left unterminated to decrease supply current. 56 gnd ground. 0 volt 57 vcc positive analog power supply. +3.3 v 10%. 58 59 c622on-b c622op-b c622 clock output (lvpecl) . these outputs provide a differential lvpecl clock at 622.08 mhz. unused lvpec l port should be left unterminated to decrease supply current. pin description table (continued) pin # name description
zl30414 data sheet 5 zarlink semiconductor inc. 1.0 functional description the zl30414 is an analog phased-locked loop which prov ides rate conversion and jitter attenuation for sonet/sdh oc-192/stm-64, oc-48/st m-16, oc-12/stm-4 and oc-3/stm-1 applications. a functional block diagram of the zl30414 is shown in figure 1 and a brie f description is presented in the following sections. 1.1 frequency/phase detector the frequency/phase detector compares the frequency/p hase of the input referenc e signal with the feedback signal from the frequency divider circuit and provides an error signal corresponding to the frequency/phase difference between the two. this error signal is passed to the loop filter circuit. 1.2 lock indicator the zl30414 has a built-in lock detector that measures frequency difference between input reference clock c19i and the vco frequency. when the vco frequency is less than 300 ppm apart from the input reference frequency then the lock pin is set high. the lock pin is pu lled low if the frequency difference exceeds 1000 ppm. 1.3 loop filter the loop filter is a low pass filter. this low pass filter ensures that the network jitter requirements are met for an input reference frequency of 19.44 mhz. the corner frequency of the loop filter is configurable with an external capacitor and resistor connected to the lp f pin and ground as shown in figure 3. figure 3 - loop filter elements 60 gnd ground. 0 volt 61 vcc positive analog power supply. +3.3 v 10%. 62 63 c622op-a c622on-a c622 clock output (lvpecl) . these outputs provide a differential lvpecl clock at 622.08 mhz. unused lvpec l port should be left unterminated to decrease supply current. 64 gnd ground. 0 volt 65 nc no internal bonding connection. leave unconnected. pin description table (continued) pin # name description r f c f zl30414 lpf r f =8.2 k ?, c f =470 nf filter loop frequency and phase detector vco
zl30414 data sheet 6 zarlink semiconductor inc. 1.4 vco the voltage-controlled oscillator (vco) receives the fi ltered error signal from the loop filter, and based on the voltage of the error signal generates a primary frequency. the vco output is connected to the "frequency dividers and clock drivers" block that divides vco frequency and buffer generated clocks. 1.5 output interface circuit the output of the vco is used by the output interfac e circuit to provide four l vpecl differential clocks at 622.08 mhz, one cml differential clock at 155.52 mhz and a single-ended 19.44 mhz output clock. this block provides also a 19.44 mhz feedback clock that closes pll loop. each output clock can be enabled or disabled individually with the a ssociated output enable pin. to reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be disabled. if any of the lvpecl outp uts are disabled they must be le ft open without any terminations. output clocks output enable pins c622op/n-a c622oen-a c622op/n-b c622oen-b c622op/n-c c622oen-c c622op/n-d c622oen-d c155op/n c155oen c19o c19oen table 1 - output enable control
zl30414 data sheet 7 zarlink semiconductor inc. 2.0 zl30414 performance the following are some of the zl30414 performance indicators that complement results lis ted in the characteristics section of this data sheet. 2.1 input jitter tolerance jitter tolerance is a measure of the pll?s ability to operat e properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its input reference. the input jitter tolerance of the zl30414 is shown in figure 4. on this graph, the single line at the top represents measured input jitter tolerance and the three overlapping li nes below represent minimum input jitter tolerance for oc-192, oc-48, and oc-12 network in terfaces. the jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interf aces operating at different rates. figure 4 - input jitter tolerance
zl30414 data sheet 8 zarlink semiconductor inc. 2.2 jitter transfer characteristic jitter transfer characteristic represents a ratio of the jitter at the output of a p ll to the jitter applied to the input of a pll. this ratio is expressed in db and it characterizes th e plls ability to attenuate (fil ter) jitter. the jitter transfer characteristic for the zl30414 configured with recommended loop filter components (r f =8.2 k ?, c f =470 nf) is shown in figure 5. the plotted curves represent jitter transfer characteristics over the recommended voltage (3.0 v to 3.6 v) and temperature (-40c to 85c) ranges. figure 5 - jitter tr ansfer characteristic
zl30414 data sheet 9 zarlink semiconductor inc. 3.0 applications 3.1 ultra-low jitter sonet/sdh equipment clocks the zl30414 functionality and performance complements t he entire family of the zarlink?s advanced network synchronization plls. its superior ji tter filtering characteristics exceed requirements of sonet/sdh optical interfaces operating up to oc-192/stm-64 rate (10 gbit/s ). the zl30414 in combinatio n with the mt90401 or the zl30407 (sonet/sdh network element plls) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see figure 6) . figure 6 - sonet/sdh equipment clock mt90401 zl30414 c155o cml 622.08 mhz 19.44 mhz c622oa lvpecl c622ob lvpecl c622oc lvpecl c622od lvpecl c19o cmos c19i c19o cmos c155o lvds c34o/c44o cmos c16o cmos c8o cmos c6o cmos 19.44 mhz c2o cmos c1.5o cmos f8o cmos f0o cmos 622.08 mhz 622.08 mhz 622.08 mhz 155.52 mhz c4o cmos 34.368 mhz or 44.736 mhz 16.384 mhz 8.192 mhz 6.312 mhz 4.096 mhz 2.048 mhz 1.544 mhz 8 khz 8 khz pri sec prior secor lock holdover refsel refalign r f lpf c f c 1 5 5 o e n 155.52 mhz c 6 2 2 o e n - a c 6 2 2 o e n - b c 6 2 2 o e n - c c 6 2 2 o e n - d c 1 9 o e n d s c s r / w a 0 - a 6 d 0 - d 7 up data port controller port synchronization reference clocks note: only main functional connections are shown 20 mhz c 2 0 i f16o cmos ocxo 8 khz or zl30407 l o c k
zl30414 data sheet 10 zarlink semiconductor inc. the zl30414 in combination with the mt9046 provides an optimum solution for sonet/sdh line cards (see figure 7). figure 7 - sonet/sdh line card mt9046 zl30414 c19i c19o cmos c16o cmos c8o cmos c6o cmos 19.44 mhz c2o cmos c1.5o cmos f8o cmos f0o cmos c4o cmos 16.384 mhz 8.192 mhz 6.312 mhz 4.096 mhz 2.048 mhz 1.544 mhz 8 khz 8 khz pri sec lock holdover rsel r 1 lpf c 1 c 1 5 5 o e n c 6 2 2 o e n - a c 6 2 2 o e n - b c 6 2 2 o e n - c c 6 2 2 o e n - d c 1 9 o e n m s 1 f s 2 f l o c k uc synchronization reference clocks note: only main functional connections are shown 20 mhz f16o cmos tcxo 8 khz c 2 r 1 = 680 ? c 1 = 820 nf c 2 = 22 nf c20i m s 2 f s 1 p c c i hardware control t c l r c155o cml 622.08 mhz 19.44 mhz c622oa lvpecl c622ob lvpecl c622oc lvpecl c622od lvpecl c19o cmos 622.08 mhz 622.08 mhz 622.08 mhz 155.52 mhz l o c k
zl30414 data sheet 11 zarlink semiconductor inc. 3.2 recommended interface circuit 3.2.1 lvpecl to lvpecl interface the c622op/n-a, c622op/n-b, c622op/n-b, and c622op/ n-d outputs provide differential lvpecl clocks at 622.08 mhz. the lvpecl out put drivers require a 50 ? termination connected to the vcc-2v source for each output terminal at the terminating end as shown below. the terminating resistors should be placed as close as possible to the lvpecl receiver. figure 8 - lvpecl to lvpecl interface 3.2.2 cml to cml interface the c155o output provides a differentia l cml/lvds compatible clock at 155. 52 mhz. the output drivers require a 50 ? load at the terminating end if the receiver is cml type. figure 9 - cml to cml interface lvpecl lvpecl zl30414 z=50 ? z=50 ? c622op-a c622on-a receiver gnd typical resistor values: r1 = 130 ? , r2 =82 ? r1 r2 vcc=+3.3v r1 r2 vcc 0.1uf +3.3v driver 622.08 mhz zl30414 cml z=50 ? cml 50 ? c155op c155on driver gnd vcc receiver 0.1uf +3.3v 50 ? z=50 ? 0.1uf 0.1uf low impedance dc bias source 155.52 mhz
zl30414 data sheet 12 zarlink semiconductor inc. 3.2.3 cml to lvds interface to configure the driver as an lvds driver, external biasing resistors are required to set up the common mode voltage as specified by ansi/tia/eia-644 lvds standard. the standard specifies the v cm (common mode voltage) as minimum 1.125 v, typical 1.2 v, and maximum 1.375 v . the following figure provides a recommendation for lvds applications. figure 10 - lvds termination 3.2.4 cml to lvpecl interface the cml output can drive lvpecl input as is shown in figure 11. the terminating resistors should be placed as close as possible to the lvpecl receiver. figure 11 - cml to lvpecl interface zl30414 cml z=50 ? z=50 ? driver 0.1uf +3.3v gnd vcc lvds 10nf 10nf receiver r1 r2 vcc=+3.3v r1 r2 100 ? typical resistor values: r1 = 16 k ?, r2 = 10 k ? c155op c155on 155.52 mhz lvpecl cml zl30414 z=50 ? z=50 ? receiver gnd typical resistor values: r1 = 82 ? , r2 =130 ? r1 r2 vcc=+3.3v r1 r2 vcc 0.1uf +3.3v driver 10nf 10nf c155op c155on 155.52 mhz
zl30414 data sheet 13 zarlink semiconductor inc. 3.3 tristating lvpecl outputs the zl30414 has four differential 622.08 mhz lvpecl outputs, which can be used to drive four different oc-3/oc- 12/oc-48/oc-192 devices such as framer s, mappers and serdes. in the case where fewer than four clocks are required, a user can dis able unused lvpecl outputs on the zl30414 by pu lling the corresponding enable pins low. when disabled, voltage at the both pins of the differential lvpecl output will be pulled up to vcc - 0.7 v. for applications requiring the lvpecl outputs to be in a tri-state mode, external ac coupling can be used as shown in figure 12. typically this might be required in hot swappable applications. resistors r1 and r2 are required for dc bias of the lvpecl driver. capacitors c1 and c2 are used as ac coupling capacitors. during disable mode (c622oen pin pull ed low) those capacitors present infinite impedance to the dc signal and to the receiving device this looks like a tristated (high-z) output. resistors r3, r4, r5 and r6 are used to terminate the transmission line with 50 ohm impedance and to generate dc bias voltage for the lvpecl receiver. if the lvpecl receiver has an integrat ed 50 ohm termination and bias source, resistors r3, r4, r5 and r6 should not be populated. figure 12 - tristatable lvpecl outputs z=50 z=50 c622oen zl30414 0.1u c1 0.1u c2 r4 82.5 r6 82.5 r5 127 r3 127 r1 200 r2 200 3.3v 3.3v
zl30414 data sheet 14 zarlink semiconductor inc. 3.4 power supply and bias circuit filtering recommendations figure 13 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. the level of required f iltering is subject to further optimi zation and simplification. please check zarlink?s web site for updates. figure 13 - power supply and bias circuit filtering 50 52 54 56 58 60 62 64 34 40 44 46 48 42 32 30 28 26 24 22 20 18 gnd vdd gnd vcc vdd vdd gnd gnd gnd gnd vcc vdd vdd vdd gnd vcc gnd vcc gnd vcc gnd vcc 16 14 12 10 6 4 2 8 gnd vcc1 gnd vcc2 gnd gnd gnd gnd gnd gnd 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf ferrite bead 0.1uf 33uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf notes: 1. all the ground pins (gnd) and the exposed die pad (metal area at the back of the package) are connected to the same ground p lane. 2. select ferrite bead with i dc > 400 ma and r dc in a range from 0.10 ? to 0.15 ? +3.3v power rail zl30414 0.1uf gnd gnd bias 220 ? 11 vcc 0.1uf 36 38 + 0.1uf 4.7 ? 10uf + + 33uf + 33uf 0.1uf 0.1uf vdd
zl30414 data sheet 15 zarlink semiconductor inc. 4.0 characteristics ? voltages are with respect to ground unless otherwise stated. ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? voltages are with respect to ground unless otherwise stated. ? typical figures are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings ? characteristics sym. min. ? max. ? units 1 supply voltage v ddr , v ccr tbd tbd v 2 voltage on any pin v pin -0.5 v cc + 0.5 v dd + 0.5 v 3 current on any pin i pin -0.5 30 ma 4 esd rating v esd 1250 v 5 storage temperature t st -55 125 c 6 package power dissipation p pd 1.8 w recommended operating conditions ? characteristics sym. min. typ. ? max. units notes 1 operating temperature t op -40 25 +85 c 2 positive supply v dd , v cc 3.0 3.3 3.6 v dc electrical characteristics ? characteristics sym. min. typ. ? max. units notes 1 supply current i dd +i cc 146 ma lvpecl, cml drivers disabled and unterminated 2 incremental supply current to single lvpecl driver (driver enabled and terminated, see figure 8) i lvpecl 37 ma note 1 note 2 3 incremental supply current to cml driver (driver enabled and terminated, see figure 9) i cml 26 ma note 3 4 cmos: high-level input voltage v ih 0.7v dd v dd v 5 cmos: low-level input voltage v il 00.3v dd v 6 cmos: input leakage current i il 15uav i = v dd or 0 v
zl30414 data sheet 16 zarlink semiconductor inc. - ? : voltages are with respect to ground unless otherwise stated. - ? :typical figures are for design aid only: not guaranteed and not subject to production testing. - supply voltage and operating temperature are as per recommended operating conditions - note 1: the i lvpecl current is determined by the termination networ k connected to lvpecl outputs. mo re than 25% of this current flows outside the chip and it does not contribute to the internal power dissipation. - note 2: lvpecl outp uts terminated with z t = 50 ? resistors biased to v cc -2v (see figure 8) - note 3: cml outputs terminated with z t = 50 ? resistors connected to low impedance dc bias voltage source (see figure 9) 7 cmos: input bias current for pulled-down inputs: c622oen-a, c622oen-c, c622oen-d, oc-clkoen i b-pu 300 ua v i = v dd 8 cmos: input bias current for pulled-up inputs: , c622oen-b, c19oen i b-pd 90 ua v i = 0v 9 cmos: high-level output voltage v oh 2.4 v i oh = 8 ma 10 cmos: low-level output voltage v ol 0.4 v i ol = 4 ma 11 lock pin: high-level output voltage v oh 2.4 i oh = 0.5 ma 12 lock pin: low-level output voltage v ol 0.4 i ol = 0.5 ma 13 cmos: c19o output rise time t r 1.8 3.3 ns 18 pf load 14 cmos: c19o output fall time t f 1.1 1.4 ns 18 pf load 15 lvpecl: differential output voltage (622.08 mhz) iv od_lvpecl i 1.17 v note 2 16 lvpecl: offset voltage (622.08 mhz) v os_lvpecl vcc- 1.31 vcc- 1.20 vcc- 1.09 v note 2 17 lvpecl: output rise/fall times (622.08 mhz) t rf 170 ps note 2 18 cml: differential output voltage (155.52 mhz) iv od_cml i 0.73 v note 3 19 cml: offset voltage (155.52 mhz) v os_cml vcc- 0.58 vcc- 0.54 vcc- 0.50 v note 3 20 cml: output rise/fall times (155.52 mhz) t rf 220 ps note 3 dc electrical characteristics ? (continued) characteristics sym. min. typ. ? max. units notes
zl30414 data sheet 17 zarlink semiconductor inc. ? voltages are with respect to ground unless otherwise stated. figure 14 - output timing parameter measurement voltage levels ac electrical characteristics ? - output timing parameters measurement voltage levels characteristics sym cmos lvpecl cml units 1 threshold voltage v t-cmos v t-lvpecl v t-cml 0.5v dd 0.5v od_lvpecl 0.5v od_cml v 2 rise and fall threshold voltage high v hm 0.7v dd 0.8v od_lvpecl 0.8v od_cml v 3 rise and fall threshold voltage low v lm 0.3v dd 0.2v od_lvpecl 0.2v od_cml v v t all signals v hm v lm t if , t of t ir , t or timing reference points
zl30414 data sheet 18 zarlink semiconductor inc. ? supply voltage and operating temperature are as per recommended operating conditions ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 15 - c19i input to c19o, c155o and c622o output timing ac electrical ch aracteristics ? - c19i input to c19o, c155o and c622o output timing characteristics sym. min. typ. ? max. units notes 1 c19i to c19o delay t c19d 6.2 7.2 8.2 ns 2 c19i to c155o delay tc 155d 345ns 3 c19i to c622oa delay t c622d 00.81.6ns 4 c155o duty cycle d c155l 48 50 52 % 5 c622o duty cycle d c622l 48 50 52 % c622oa v t-lvpecl c19i v t-cmos (19.44 mhz) t c19d c19o v t-cmos (19.44 mhz) t c622d (622.08 mhz) c155o v t-cml t c155d (155.52 mhz)
zl30414 data sheet 19 zarlink semiconductor inc. ? supply voltage and operating temperature are as per recommended operating conditions ? typical figures are for design aid only: not guaranteed and not subject to production testing. figure 16 - c622ob, c622oc, c622od outputs timing ac electrical characteristics ? - c622 clocks output timing characteristics sym. min. typ. ? max. units notes 1 c622oa to c622ob t c622d-ab -50 0 +50 ps 2 c622oa to c622oc t c622d-ac -50 0 +50 ps 3 c622oa to c622od t c622d-ad -50 0 +50 ps c622od v t-lvpecl c622oc t c622d-ab c622ob c622oa v t-lvpecl v t-lvpecl v t-lvpecl t c622d-ac t c622d-ad note: all output clocks have nominal 50% duty cycle.
zl30414 data sheet 20 zarlink semiconductor inc. performance characteristics - functional (v cc = 3.3 v 10%; t a = -40 to 85 c ) performance characteristics : output jitter generation - gr-253-core conformance (v cc = 3.3v 10%; t a = -40 to 85 c ) ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f =8.2 k ?, c f =470 nf characteristics min. typ. max. units notes 1 pull-in range 1000 ppm at nominal input reference frequency c19i = 19.44 mhz 2 lock time 300 ms gr-253-core jitter generation requirements zl30414 jitter generation performance interface (category ii) jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units 1 oc-192 sts-192 50 khz - 80 mhz 0.1 ui pp 10.0 - 7.31 ps p-p 0.01 ui rms 1.0 0.52 0.94 ps rms 2oc-48 sts-48 12 khz - 20 mhz 0.1 ui pp 40.2 - 7.32 ps p-p 0.01 ui rms 4.02 0.58 0.83 ps rms 3oc-12 sts-12 12 khz - 5 mhz 0.1 ui pp 161 - 4.37 ps p-p 0.01 ui rms 16.10.340.60ps rms
zl30414 data sheet 21 zarlink semiconductor inc. performance characteristics : output jitter generation - g.813 conformance (option 1 and 2) (v cc = 3.3v 10%; t a = -40 to 85 c ) ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f =8.2 k ?, c f =470 nf g.813 jitter generation requirements zl30414 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units option 1 1 stm-64 4 mhz to 80 mhz 0.1 uipp 10.0 - 6.95 ps p-p 0.49 0.89 ps rms 20 khz to 80 mhz 0.5 uipp 50.2 - 11.5 ps p-p 0.82 1.04 ps rms 2 stm-16 1 mhz to 20 mhz 0.1 uipp 40.2 - 6.40 ps p-p 0.50 0.68 ps rms 5 khz to 20 mhz 0.5 uipp 201 - 8.67 ps p-p 0.68 1.06 ps rms 3 stm-4 250 khz to 5 mhz 0.1 uipp 161 - 3.33 ps p-p 0.26 0.42 ps rms 1 khz to 5 mhz 0.5 uipp 804 - 19.1 ps p-p 1.51 2.88 ps rms option 2 5 stm-64 4 mhz to 80 mhz 0.1 uipp 10.0 - 6.95 ps p-p 0.49 0.89 ps rms 20 khz to 80 mhz 0.3 uipp 30.1 - 11.5 ps p-p 0.82 1.04 ps rms 6 stm-16 12 khz - 20 mhz 0.1 uipp 40.2 - 7.32 ps p-p 0.58 0.83 ps rms 7 stm-4 12 khz - 5 mhz 0.1 uipp 161 - 4.37 ps p-p 0.34 0.60 ps rms
zl30414 data sheet 22 zarlink semiconductor inc. performance characteristics : output jitter generation - etsi en 300 462-7-1conformance (v cc = 3.3v 10%; t a = -40 to 85 c ) ? typical figures are for design aid only: not guaranteed and not subject to production testing. ? loop filter components: r f =8.2 k ?, c f =470 nf en 300 462-7-1 jitter generation requirements zl30414 jitter generation performance interface jitter measurement filter limit in ui equivalent limit in time domain typ. ? max. ? units 1 stm-16 1 mhz to 20 mhz 0.1 uipp 40.2 - 6.40 ps p-p 0.50 0.68 ps rms 5 khz to 20 mhz 0.5uipp 201 - 8.67 ps p-p 0.68 1.06 ps rms 2 stm-4 250 khz to 5 mhz 0.1 uipp 161 - 3.33 ps p-p 0.26 0.42 ps rms 1 khz to 5 mhz 0.5 uipp 804 - 19.1 ps p-p 1.51 2.88 ps rms
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of ZL30414QGC

	To Download ZL30414QGC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .